-- Licznik programu (modulo 9)
-- Wyjscie: OUTPUT[3..0]
-- Wejscia sterujace:
-- RESET# (reset)
-- INCR#  (increment)
-- CLOCK<

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all; 

entity PROG_COUNTER is
  generic (delay : time := 5 ns);
  port (RESET  : in std_logic;
        INCR   : in std_logic;
        CLOCK  : in std_logic;
        OUTPUT : out std_logic_vector(3 downto 0));
end entity PROG_COUNTER;

architecture PROG_COUNTER_arch of PROG_COUNTER is
begin
  process(RESET, CLOCK)
    variable state : integer range 0 to 8;
  begin
      if(RESET = '0') then
        OUTPUT <= "0000" after delay;
        state := 0;
      elsif (INCR = '0' and falling_edge(CLOCK)) then
        state := (state + 1) mod 9;
        OUTPUT <= conv_std_logic_vector(state, 4) after delay;
      end if;
  end process;
end architecture PROG_COUNTER_arch;
